How many faults can there be with 7 ic’s…
Today we finally got around to do the rest of the testing on the IRQ prototype board, in order to be able to get the stage2 board. There were some more difficulties (mostly bad thinking from our side) but we managed to get it running with some small modifications. So now, with some minor updates we are able to order a batch of stage2 boards. One major step towards the complete system.
And you know what? I was actually contacted by a representative from PCBWay who showed interest in this project, so now they are actually sponsoring it! I’m really looking forward to this! I will get back on this.
So what did we need to update further after some more prototype testing?
Well after the Q debacle yesterday we found that the output (the IRQ signal) is active high and the processor expects an active low signal, so here we got to insert the extra unused NOR-gate to invert it.
OE was also connected to the read signal and since it is an active low input it needed to be inverted. So we reused the NOR-gate used for the previously used clock pulse.
We also found that the NAND gates collecting the irq-levels (U5) was out of order so the interrupts came in in the wrong order.
But with all these fixes we have now pressad the order button for stage 2!
